The present invention relates to the fabrication of integrated circuits. More particularly, the present invention is directed toward methods for providing self-planarized deposition of high quality dielectric layers for shallow trench isolation.
Semiconductor device geometries continue to decrease in size, providing more devices per unit area on a fabricated wafer. These devices are typically initially isolated from each other as they are built into the wafer, and they are subsequently interconnected to create the specific circuit configurations desired. Currently, some devices are fabricated with feature dimensions as small as, or smaller than, 0.18 μm. For example, spacing between devices such as conductive lines or traces on a patterned wafer may be separated by 0.18 μm leaving recesses or gaps of a comparable size. A nonconductive layer of dielectric material, such as silicon dioxide (SiO2), is typically deposited over the features to fill the aforementioned gaps and insulate the features from other features of the integrated circuit in adjacent layers or from adjacent features in the same layer.
Dielectric layers are used in various applications including shallow trench isolation (STI) dielectric for isolating devices and interlayer dielectric (ILD) formed between metal wiring layers or prior to a metallization process. In some cases, STI is used for isolating devices having feature dimensions of 0.5 μm or smaller. Planarization of dielectric layers has become increasingly important as the packing densities of semiconductor devices continue to grow.
The planarization issue is described using an example of a typical process for forming a shallow trench isolation (commonly referred to as STI integration) as illustrated in FIGS. 1A-1G. In FIG. 1A, a silicon substrate 110 has deposited thereon a pad oxide layer 112 and a nitride layer 114 such as silicon nitride. The nitride layer 114 is typically deposited by low pressure chemical vapor deposition (LPCVD), and serves as an etch stop for chemical mechanical polishing (CMP). Referring to FIG. 1B, a bottom anti-reflective coating (BARC) 116 is formed above the nitride layer 114 for absorbing light reflected from the substrate 110 during photolithography. Typically an organic spin-on glass (SOG), the BARC 116 is needed typically for light having wavelengths of below about 248 nm, including deep ultraviolet (DUV) and far ultraviolet (FUV) light. A photoresist 118 is formed over the BARC 116 and exposed using a mask (not shown) which defines the location of the trenches. The exposed photoresist is then stripped to leave open areas for forming the trenches. Typically, a plasma etch is performed to etch the open areas through the nitride 114, pad oxide 112, and silicon substrate 110 to form the trenches 120, as shown in FIG. 1C. After the remaining photoresist 118 and BARC 116 are removed, a thermal oxide 122 is typically grown on the nitride/pad oxide and on the surfaces of the trenches 120 (trench bottom 124 and trench wall 126) to repair the plasma damage to the silicon substrate 110, as illustrated in FIG. 1D.
A dielectric layer 128 is then deposited over the thermal oxide 122 to fill the trenches 120 and cover the nitride layer 114. This dielectric layer 128 is often referred to as a trench oxide filling layer. Typical dielectric layers are formed from oxide materials such as silicon dioxide or silicate glass. As shown in FIG. 1E, the surface profile of the deposited dielectric layer 128 is stepped and generally resembles the shape of the trenched substrate 110. The surface profile is more uniform in dense fields with closely space narrow trenches than in open fields with wide trenches. As seen in FIG. 1E, a step height 130 is formed in the dielectric profile between the dense field 134 and the open field 132. Because of the step height 130, it is not practicable to apply CMP directly after the dielectric layer deposition step to planarize the dielectric layer 128 because otherwise a dishing effect in the open field 132 will result with CMP, as seen in FIG. 1H. Instead, a reverse mask and etch procedure is used to etch the extra oxide to obtain a more planar surface profile as illustrated in FIG. 1F. This procedure typically involves the steps of photoresist deposit, reverse masking, cure, etched photoresist removal, etchback, and removal of remaining photoresist. A CMP procedure is then applied to the structure of FIG. 1F to globally planarize the surface of the filled substrate 110 as shown in FIG. 1G. The reverse mask and etch procedure necessitated by the step height effect adds significant cost and complexity (for example, due to the added lithography steps involved) to the planarization procedure.
From the discussion above, it is seen that multiple steps, including additional photolithography steps (which require expensive equipment), are needed to provide STI. However, it is desirable to reduce the number of steps (and related equipment, especially photolithography equipment which requires expensive lenses, light sources, etc.) and to obtain improved results in order to provide a more economic and efficient manufacturing process. For example, one way to obtain improved results is to provide a self-planarized, high quality trench oxide filling layer at a reduced cost.
A number of procedures are known for depositing dielectric layers such as the gap-fill dielectric 128 for the trench oxide filling layer in the example shown in FIG. 1E. One type of process employs O3 (ozone) and TEOS (tetraethylorthosilicate) for depositing a dielectric film such as silicate glass. Such films deposited are commonly referred to as “O3/TEOS films”. O3/TEOS processes have a surface sensitivity which increases as the O3/TEOS ratio increases. Due to the surface sensitivity, the dielectric deposition rate varies in accordance with the properties of the material of the underlying layer.
It is known to minimize the surface sensitivity by depositing a surface insensitive barrier layer prior to the O3/TEOS film deposition. One known method is to lower the surface sensitivity by decreasing the O3/TEOS ratio and/or decreasing the pressure. However, lowering the O3/TEOS ratio tends to undesirably result in a more porous dielectric film. This is particularly problematic when the dielectric film is used for isolation purposes. One way to address this concern has been to raise the process temperature to above about 500 degrees Celsius, but raising the process temperature is often undesirable. Alternatively, an additional anneal process after the deposition of the trench oxide filling layer has been used to densify the trench oxide filling layer. This method, however, suffers from the need to perform an extra step.
Instead of minimizing the surface sensitivity, some have utilized the deposition rate dependence of O3/TEOS films to perform gap fill for a trenched silicon substrate wherein the side walls of the trench are covered with thermal oxide spacers. Using an atmospheric pressure CVD (APCVD) O3/TEOS deposition and an ozone concentration of 5%, it was reported that faster film growth on the bottom silicon than on the side wall spacers precluded void formation to achieve void-free gap fill. Others have investigated the feasibility of forming a planarized intermetal dielectric (IMD) by taking advantage of the surface sensitivity of O3/TEOS and similar materials such as O3-octamethylcyclotetrasiloxane (OMTC). Researchers have reported difficulties of controlling the different deposition rates to achieve planarity. For instance, significant elevations have been observed at the edges of aluminum metal lines caused by the different deposition rates of the O3/TEOS on a TiN ARC layer on top of the aluminum and the aluminum side walls. Some of these same researchers have reported more satisfactory planarization results for depositing SiO2 layers on an aluminum interconnect built upon a phosphorus glass (PSG) level using O3—OMTC.
In investigating sub atmospheric chemical vapor deposition (SACVD) of TEOS/O3 for self-planarized shallow trench isolation (STI) applications, the inventors also encountered difficulties in trench fill quality. As shown in FIG. 2A, porous regions 140 developed in the trench fill dielectric generally adjacent the nitride layer. It is believed these regions 140 were caused by faster deposition rates (up to 5 times faster) of TEOS/O3 on the silicon substrate (i.e., the trench bottom and walls) than on nitride layer 114.
After CMP of nitride layer 114 and pad oxide 112, the trench fill material 128 is undercut near the trench corners as shown in FIG. 2B. The eroded trench corners 142 may lead to an undesirable electrostatic field between adjacent active regions notwithstanding the underlying STI.
What is needed are more efficient and economic methods for self-planarized deposition of a high quality trench oxide filling layer for shallow trench isolation integration. Improved methods of effectively utilizing the deposition rate dependence of dielectric materials such as O3/TEOS films are also desired. It also would be desirable to provide self-planarized STI without the corner erosion problems depicted in FIG. 2.